The present invention relates to a semiconductor memory device and a semiconductor integrated circuit device which include a memory cell requiring refresh for holding data.
To hold data of a memory cell, DRAMs require a refresh operation. A DRAM disclosed in Reference 1 (Japanese Laid-Open Publication No. 11-339468 (FIG. 3) is capable of performing an auto-refresh operation by a refresh request signal from the outside and a self-refresh operation by setting the DRAM to be a self-refresh mode for performing refresh using an internal timer.
In an auto-refresh operation, in an interval between read/write operations, a refresh request signal has to be generated outside of the DRAM and supplied to the DRMA so that a refresh operation is performed for a predetermined number of times in every given period.
In a self-refresh operation, a refresh operation of the DRAM is started based on the internal timer. Therefore, it is not necessary to externally generate a timing signal for each individual refresh operation. However, a read/write access from the outside is not allowed in a period in which the DRAM is in a self-refresh mode.
Moreover, in Reference 2 (Japanese Laid-Open Publication No. 2001-210074 (FIG. 3)), disclosed is a technique for detecting that there is no request for a read/write operation from the outside and internally generating a refresh control signal in the DRAM to automatically perform refresh. Furthermore, a technique for performing, if the internal refresh operation has been performed for necessary times in a predetermined period, a control so that no more refresh operation is performed, in order to reduce consumption power is also disclosed.
In Reference 3 (Japanese Laid-Open Publication No. 2002-175691 (FIG. 4), disclosed is a DRAM which performs, when a read/write operation is commanded from the outside, a refresh operation in a read/write cycle of the commanded read/write operation before an actual read/write processing is performed. With this DRAM, it is not necessary to externally generate a refresh request signal and stop a read/write operation to insert a refresh operation. Therefore, a data transfer rate can be increased.